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12-bit rdc with reference oscillator ad2s1205 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features complete monolithic resolver-to-digital converter (rdc) parallel and serial 12-bit data ports system fault detection 11 arc minutes of accuracy input signal range: 3.15 v p-p 27% absolute position and velocity outputs 1250 rps maximum tracking rate, 12-bit resolution incremental encoder emulation (1024 pulses/rev) programmable sinusoidal oscillator on board single-supply operation (5.00 v 5%) ?40c to +125c temperature rating 44-lead lqfp 4 kv esd protection qualified for automotive applications applications automotive motion sensing and control hybrid-electric vehicles electric power steering integrated starter generator/alternator industrial motor control process control functional block diagram 06339-001 reference oscillator (dac) type ii tracking loop fault detection position register reset ad2s1205 data bus output velocity register encoder emulation synthetic reference internal clock generator voltage reference reference pins cr y st a l data i/o adc adc multiplexer excitation outputs inputs from resolver fault detection outputs encoder emulation outputs figure 1. general description the ad2s1205 is a complete 12-bit resolution tracking resolver-to-digital converter that contains an on-board programmable sinusoidal oscillator providing sine wave excitation for resolvers. the converter accepts 3.15 v p-p 27% input signals on the sin and cos inputs. a type ii tracking loop is employed to track the inputs and convert the input sin and cos information into a digital representation of the input angle and velocity. the maximum tracking rate is a function of the external clock frequency. the performance of the ad2s105 is specified across a frequency range of 8.192 mhz 25%, allowing a maximum tracking rate of 1250 rps. product highlights 1. ratiometric tracking conversion. the type ii tracking loop provides continuous output position data without conversion delay. it also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. 2. system fault detection. a fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking. 3. input signal range. the sin and cos inputs can accept differential input voltages of 3.15 v p-p 27%. 4. programmable excitation frequency. excitation frequency is easily programmable to 10 khz, 12 khz, 15 khz, or 20 khz by using the frequency select pins (the fs1 and fs2 pins). 5. triple format position data. absolute 12-bit angular position data is accessed via either a 12-bit parallel port or a 3-wire serial interface. incremental encoder emulation is in standard a-quad-b format with direction output available. 6. digital velocity output. 12-bit signed digital velocity accessed via either a 12-bit parallel port or a 3-wire serial interface.
ad2s1205 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 resolver format signals ................................................................... 8 theory of operation ........................................................................ 9 fault detection circuit ................................................................ 9 monitor signal .............................................................................. 9 loss of signal detection .............................................................. 9 signal degradation detection .................................................. 10 loss of position tracking detection ........................................ 10 responding to a fault condition ............................................. 10 false null condition .................................................................. 10 on-board programmable sinusoidal oscillator .................... 11 synthetic reference generation ............................................... 11 charge-pump output ................................................................ 11 connecting the converter ........................................................ 11 clock requirements ................................................................... 12 absolute position and velocity output ................................... 12 parallel interface ......................................................................... 12 serial interface ............................................................................ 14 incremental encoder outputs .................................................. 16 supply sequencing and reset ................................................... 16 circuit dynamics ........................................................................... 17 loop response model ............................................................... 17 sources of error .......................................................................... 18 connecting to the dsp .............................................................. 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 automotive products ................................................................. 20 revision history 5/10rev. 0 to rev. a changes to features section............................................................ 1 changes to input bias current parameter and input impedance parameter ...................................................................... 3 changes to table 2 ............................................................................ 5 changes to loss of signal detection section ................................ 9 changes to connecting the converter section and figure 5 ... 11 change to t 6 max value in table 6 ............................................... 13 changes to t 9 and t 10 max values table 7 .................................... 15 changes to ordering guide .......................................................... 20 added automotive products section .......................................... 20 1/07revision 0: initial version
ad2s1205 rev. a | page 3 of 20 specifications av dd = dv dd = 5.0 v 5% at ?40c to +125c, clkin = 8.192 mhz 25%, unless otherwise noted. table 1. parameter min typ max unit conditions/comments sin, cos inputs 1 voltage 2.3 3.15 4.0 v p-p sinusoidal waveforms, sin ? sinlo and cos ? coslo, differential inputs input bias current 12 a v in = 4.5 v dc , clkin = 10.24 mhz input impedance 0.35 m v in = 4.5 v dc common-mode voltage 100 mv peak cmv with respect to refout/2 at 10 khz phase-lock range ?44 +44 degrees sin/cos vs. exc output angular accuracy angular accuracy 11 arc minutes zero acceleration, y grade 22 arc minutes zero acceleration, w grade resolution 12 bits guaranteed no missing codes linearity inl 2 lsb zero acceleration, 0 rps to 1250 rps, clkin = 10.24 mhz linearity dnl 0.3 lsb guaranteed monotonic repeatability 1 lsb hysteresis 1 lsb velocity output velocity accuracy 2 lsb zero acceleration resolution 11 bits linearity 1 lsb guaranteed by design, 2 lsb maximum offset 0 1 lsb zero acceleration dynamic ripple 1 lsb zero acceleration dynamic performance bandwidth 1000 2400 hz tracking rate 750 rps clkin = 6.144 mhz , guaranteed by design 1000 rps clkin = 8.192 mhz , guaranteed by design 1250 rps clkin = 10.24 mhz , guaranteed by design acceleration error 30 arc minutes at 10,000 rps, clkin = 8.192 mhz settling time 179 step input 5.2 ms to within 11 arc minutes, y grade, clkin = 10.24 mhz 4.0 ms to within 1 degree, y grade, clkin = 10.24 mhz exc, exc outputs voltage 3.34 3.6 3.83 v p-p load 100 a center voltage 2.39 2.47 2.52 v frequency 10 khz fs1 = high, fs2 = high, clkin = 8.192 mhz 12 khz fs1 = high, fs2 = low, clkin = 8.192 mhz 15 khz fs1 = low, fs2 = high, clkin = 8.192 mhz 20 khz fs1 = low, fs2 = low, clkin = 8.192 mhz exc/ exc dc mismatch 35 mv thd ?58 db first five harmonics fault detec tion block loss of signal (los) sin/cos threshold 2.18 2.24 2.3 v p-p dos and lot go low when sin or cos fall below threshold angular accuracy (worst case) 57 degrees los indicated before angular output error exceeds limit (4.0 v p-p input signal and 2.18 v los threshold) angular latency (worst case) 114 degrees maximum electrical rotation before los is indicated (4.0 v p-p input signal and 2.18 v los threshold) time latency 125 s
ad2s1205 rev. a | page 4 of 20 parameter min typ max unit conditions/comments degradation of signal (dos) sin/cos threshold 4.0 4.09 4.2 v p-p dos goes low when sin or cos exceeds threshold angular accuracy (worst case) 33 degrees dos indicated before angular output error exceeds limit angular latency (worst case) 66 degrees max imum electrical rotation before dos is indicated time latency 125 s sin/cos mismatch 385 420 mv dos latched low when sin/cos amplitude mismatch exceeds threshold loss of tracking (lot) tracking threshold 5 degrees lot goes low when internal error signal exceeds threshold; guaranteed by design time latency 1.1 ms hysteresis 4 degrees guaranteed by design voltage reference refout 2.39 2.47 2.52 v i out = 100 a drift 70 ppm/c psrr ?60 db charge-pump output (cpo) frequency 204.8 khz square wave output, clkin = 8.192 mhz duty cycle 50 % power supply i dd dynamic 20 ma electrical characteristics v il , voltage input low 0.8 v v ih , voltage input high 2.0 v v ol , voltage output low 0.4 v +1 ma load v oh , voltage output high 4.0 v ?1 ma load i il , low level input current (non-pull-up) ?10 +10 a sample , cs , rdvel , clkin, soe pins i il , low level input current (pull-up) ?80 +80 a rd , fs1, fs2, reset pins i ih , high level input current ?10 +10 a i ozh , high level three-state leakage ?10 +10 a i ozl , low level three-state leakage ?10 +10 a 1 the voltages for sin, sinlo, cos, and coslo relative to agnd must be between 0.2 v and av dd .
ad2s1205 rev. a | page 5 of 20 absolute maximum ratings table 2. parameter rating supply voltage (v dd ) ?0.3 v to +7.0 v supply voltage (av dd ) ?0.3 v to +7.0 v input voltage ?0.3 v to v dd + 0.3 v output voltage swing ?0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range (ambient) ?40c to +125c storage temperature range ?65c to +150c 1 transient currents of up to 100 ma do not cause latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad2s1205 rev. a | page 6 of 20 06339-002 pin configuration and fu nction descriptions refout 44 refbyp 43 coslo 40 sinlo 38 agnd 42 agnd 36 av dd 39 exc 35 exc 34 cos 41 sin 37 dv dd 1 rd 2 cs 3 sample 4 rdvel 5 soe 6 db11/so 7 db10/scl k 8 db9 9 db8 10 db7 11 reset 33 fs2 32 fs1 31 lot 30 dos 29 ad2s1205 top view (not to scale) dir 28 nm 27 b 26 a 25 cpo 24 dgnd 23 db6 12 db5 13 db4 14 db3 15 dgnd 16 dv dd 17 db2 18 db1 19 db0 20 x tal out 21 clkin 22 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 17 dv dd digital supply voltage, 4.75 v to 5.25 v. this is the su pply voltage for all digital circuitry on the ad2s1205. the av dd and dv dd voltages ideally should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 2 rd edge-triggered logic input. this pin acts as a frame sy nchronization signal and output enable. the output buffer is enabled when cs and rd are held low. 3 cs chip select. active low logic input. the device is enabled when cs is held low. 4 sample sample result. logic input. data is transferred from the position and velo city integrators to the position and velocity registers, respectively, after a high-to-low transition on the sample signal. 5 rdvel read velocity. logic input. rdvel input is used to select between the an gular position register and the angular velocity register. rdvel is held high to select the angular position register and low to select the angular velocity register. 6 soe serial output enable. logic input. this pin enables either the parallel or serial interface. the serial interface is selected by holding the soe pin low, and the parallel interface is selected by holding the soe pin high. 7 db11/so data bit 11/serial data output bus. when the soe pin is high, this pin acts as db11, a three-state data output pin controlled by cs and rd . when the soe pin is low, this pin acts as so, the serial data output bus controlled by cs and rd . the bits are clocked out on the rising edge of sclk. 8 db10/sclk data bit 10/serial clock. in parallel mode this pin acts as db10, a three-state data output pin controlled by cs and rd . in serial mode this pin acts as the serial clock input. 9 to 15 db9 to db3 data bit 9 to data bit 3. three-state data output pins controlled by cs and rd . 16, 23 dgnd digital ground. these pins are ground reference points for digital circuitry on the ad2s1205. all digital input signals should be referred to this dgnd voltage. both of these pins can be connected to the agnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 18 to 20 db2 to db0 data bit 2 to data bit 0. three-state data output pins controlled by cs and rd . 21 xtalout crystal output. to achieve the specified dynamic performance, an external crystal is recommended at the clkin and xtalout pins. the position and velocity accuracy are guaranteed for a frequency range of 8.192 mhz 25%. 22 clkin clock input. to achieve the specified dynamic performance, an external crystal is recommended at the clkin and xtalout pins. the position and velocity accuracy are guaranteed for a frequency range of 8.192 mhz 25%. 24 cpo charge-pump output. analog output. a 204.8 khz square wa ve output with a 50% duty cycle is available at the cpo output pin. this square wave output can be used for ne gative rail voltage generation or to create a vcc rail. 25 a incremental encoder emulation output a. lo gic output. this output is free running and is valid if the resolver format input signals applied to the converter are valid.
ad2s1205 rev. a | page 7 of 20 pin no. mnemonic description 26 b incremental encoder emulation output b. lo gic output. this output is free running and is valid if the resolver format input signals applied to the converter are valid. 27 nm north marker incremental encoder emulation output. logic ou tput. this output is free running and is valid if the resolver format input signals applied to the converter are valid. 28 dir direction. logic output. this output is used in conjunction with the incr emental encoder emulation outputs. the dir output indicates the direction of the input rota tion and is high for increasing angular rotation. 29 dos degradation of signal. logic output. degradation of signal (d os) is detected when either resolver input (sin or cos) exceeds the specified dos sin/cos threshold. see the signal degradation detection section. dos is indicated by a logic low on the dos pin and is not latched when the input signals exceed the maximum input level. 30 lot loss of tracking. logic output. lot is indicated by a logic low on the lot pin and is not latched. see the loss of signal detection section. 31 fs1 frequency select 1. logic input. fsi in conjunction with fs2 allows the frequency of exc/ exc to be programmed. 32 fs2 frequency select 2. logic input. fs2 in conjunction with fs1 allows the frequency of exc/ exc to be programmed. 33 reset reset. logic input. the ad2s1205 requires an external reset signal to hold the reset input low until v dd is within the specified operating range of 4.5 v to 5.5 v. see the section. supply sequencing and reset 34 exc excitiation frequency. analog output. an on-board oscillator provides the sinusoidal excitation signal (exc) and its complement signal ( exc ) to the resolver. the frequency of this reference signal is programmable via the fs1 and fs2 pins. 35 exc excitation frequency complement. analog output. an on-boa rd oscillator provides the sinusoidal excitation signal (exc) and its complement signal ( exc ) to the resolver. the frequency of this reference signal is programmable via the fs1 and fs2 pins. 36, 42 agnd analog ground. these pins are ground reference points for analog circuitry on the ad2s1205. all analog input signals and any external reference signal should be referred to this agnd voltage. both of these pins should be connected to the agnd plane of a system. the agnd and dg nd voltages should ideally be at the same potential and must not be more than 0.3 v ap art, even on a transient basis. 37 sin positive analog input of differential sin/ sinlo pair. the input range is 2.3 v p-p to 4.0 v p-p. 38 sinlo negative analog input of differential sin/ sinlo pair. the input range is 2.3 v p-p to 4.0 v p-p. 39 av dd analog supply voltage, 4.75 v to 5.25 v. this pin is the supply voltage for all analog circuitry on the ad2s1205. the av dd and dv dd voltages ideally should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 40 coslo negative analog input of differential cos/coslo pair. 41 cos positive analog input of differential cos/coslo pair. 43 refbyp reference bypass. reference decoupling capacitors shou ld be connected here. typical recommended values are 10 f and 0.01 f. 44 refout voltage reference output, 2.39 v to 2.52 v.
ad2s1205 rev. a | page 8 of 20 resolver format signals 06339-003 v r = v p sin( t) v b = v s sin( t) sin( ) (a) classical resolver s1 s3 v a = v s sin( t) cos( ) s2 s4 r1 r2 v r = v p sin( t) v b = v s sin( t) sin( ) (b) variable reluctance resolver s1 s3 v a = v s sin( t) cos( ) s2 s4 r1 r2 figure 3. classical resolver vs. variable reluctance resolver a classical resolver is a rotating transformer that typically has a primary winding on the rotor and two secondary windings on the stator. a variable reluctance resolver, on the other hand, has the primary and secondary windings on the stator and no windings on the rotor, as shown in figure 3 ; however, the saliency in this rotor design provides the sinusoidal variation in the secondary coupling with the angular position. for both designs, the resolver output voltages (s3 ? s1, s2 ? s4) are as follows: sintsines1s3 0 =? )( (1) costsines4s2 0 =? )( where: is the shaft angle. sin(t) is the rotor excitation frequency. e 0 is the rotor excitation amplitude. the stator windings are displaced mechanically by 90 (see figure 3 ). the primary winding is excited with an ac reference. the amplitude of subsequent coupling onto the secondary windings is a function of the position of the rotor (shaft) relative to the stator. the resolver therefore produces two output voltages (s3 ? s1, s2 ? s4), modulated by the sine and cosine of the shaft angle. resolver format signals refer to the signals derived from the output of a resolver, as shown in equation 1. figure 4 illustrates the output format. 06339-004 0 s2 ? s4 (cosine) s3 ? s1 (sine) r2 ? r4 (reference) 90 180 270 360 figure 4. electrical resolver representation
ad2s1205 rev. a | page 9 of 20 theory of operation the ad2s1205s operation is based on a type ii tracking closed- loop principle. the digitally implemented tracking loop continually tracks the position and velocity of the resolver without the need for external convert and wait states. as the resolver moves through a position equivalent to the least significant bit weighting, the tracking loop output is updated by 1 lsb. the converter tracks the shaft angle () by producing an output angle (?) that is fed back and compared with the input angle (); the difference between the two angles is the error, which is driven towards 0 when the converter is correctly tracking the input angle. to measure the error, s3 ? s1 is multiplied by cos? and s2 ? s4 is multiplied by sin? to give s4 s2for )( s1s3for )( 0 0 ? ? sin cos tsine cossin?tsine (2) the difference is taken, giving ) ()( 0 sin cos cossin?tsine ? (3) this signal is demodulated using the internally generated synthetic reference, yielding ) ( 0 ? sincoscossine (4) equation 4 is equivalent to e 0 sin ( ? ? ), which is approximately equal to e 0 ( ? ? ) for small values of ? ? , where ? ? is the angular error. the value e 0 ( ? ? ) is the difference between the angular error of the rotor and the digital angle output of the converter. a phase-sensitive demodulator, some integrators, and a compen- sation filter form a closed-loop system that seeks to null the error signal. if this is accomplished, ? equals the resolver angle, , within the rated accuracy of the converter. a type ii tracking loop is used so that constant velocity inputs can be tracked without inherent error. for more information about the operation of the converter, see the circuit dynamics section. fault detection circuit the ad2s1205 fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking; however, the position indicated by the ad2s1205 may differ significantly from the actual shaft position of the resolver. monitor signal the ad2s1205 generates a monitor signal by comparing the angle in the position register to the incoming sin and cos signals from the resolver. the monitor signal is created in a similar fashion to the error signal (described in the theory of operation section). the incoming sin and cos signals are multiplied by the sin and cos of the output angle, respectively, and then these values are added together: ) () ( cos cos a2sinsina1 monitor + = (5) where: a1 is the amplitude of the incoming sin signal ( a1 sin ). a2 is the amplitude of the incoming cos signal ( a2 cos ). is the resolver angle. ? is the angle stored in the position register. note that equation 5 is shown after demodulation with the carrier signal sin(t) removed. also note that for a matched input signal (that is, a no fault condition), a1 is equal to a2. when a1 is equal to a2 and the converter is tracking (therefore, is equal to ?), the monitor signal output has a constant magnitude of a1 ( monitor = a1 (sin 2 + cos 2 ) = a1 ), which is independent of the shaft angle. when a1 does not equal a2, the monitor signal magnitude alternates between a1 and a2 at twice the rate of the shaft rotation. the monitor signal is used to detect degradation or loss of input signals. loss of signal detection loss of signal (los) is detected when either resolver input (sin or cos) falls below the specified los sin/cos threshold. the ad2s1205 detects this by comparing the monitor signal to a fixed minimum value. without the use of external circuitry, the ad2s1205 can detect the loss of up to three of the four connections from the resolver. the addition of two external 68 k resistors, as outlined in figure 5 , ensures that the loss of all 4 connections, that is, complete removal of the resolver, may also be detected. los is indicated by both dos and lot latching as logic low outputs. the dos and lot pins are reset to the no fault state by a rising edge of sample . the los condition has priority over both the dos and lot conditions, as shown in . los is indicated within 57 of the angular output error (worst case). table 4
ad2s1205 rev. a | page 10 of 20 signal degradation detection degradation of signal (dos) is detected when either resolver input (sin or cos) exceeds the specified dos sin/cos threshold. the ad2s1205 detects this by comparing the monitor signal to a fixed maximum value. in addition, dos is detected when the amplitudes of the sin and cos input signals are mismatched by more than the specified dos sin/cos mismatch. this is identified because the ad2s1205 continuously stores the minimum and maximum magnitude of the monitor signal in internal registers and calculates the difference between these values. dos is indicated by a logic low on the dos pin and is not latched when the input signals exceed the maximum input level. when dos is indicated due to mismatched signals, the output is latched low until a rising edge of sample resets the stored minimum and maximum values. the dos condition has priority over the lot condition, as shown in . dos is indicated within 33 of the angular output error (worst case). table 4 loss of position tracking detection loss of tracking (lot) is detected when ? t he internal error signal of the ad2s1205 exceeds 5. ? the input signal exceeds the maximum tracking rate. ? the internal position (at the position integrator) differs from the external position (at the position register) by more than 5. lot is indicated by a logic low on the lot pin and is not latched. lot has a 4 hysteresis and is not cleared until the internal error signal or internal/external position mismatch is less than 1. when the maximum tracking rate is exceeded, lot is cleared only if the velocity is less than the maximum tracking rate and the internal/external position mismatch is less than 1. lot can be indicated for step changes in position (such as after a reset signal is applied to the ad2s1205), or for accelerations of >~65,000 rps 2 . it is also useful as a built-in test to indicate that the tracking converter is functioning properly. the lot condition has lower priority than both the dos and los conditions, as shown in . the lot and dos conditions cannot be indicated at the same time. tabl e 4 table 4. fault detection decoding condition dos pin lot pin order of priority loss of signal (los) 0 0 1 degradation of signal (dos) 0 1 2 loss of tracking (lot) 1 0 3 no fault 1 1 responding to a fault condition if a fault condition (los, dos, or lot) is indicated by the ad2s1205, the output data is presumed to be invalid. even if a reset or sample pulse releases the fault condition and is not immediately followed by another fault, the output data may be corrupted. as discussed previously, there are some fault conditions with inherent latency. if the device fault is cleared, there may be some latency in the resolvers mechanical position before the fault condition is reindicated. when a fault is indicated, all output pins still provide data, although the data may or may not be valid. the fault condition does not force the parallel, serial, or encoder outputs to a known state. response to specific fault conditions is a system-level requirement. the fault outputs of the ad2s1205 indicate that the device has sensed a potential problem with either the internal or external signals of the ad2s1205. it is the responsibility of the system designer to implement the appropriate fault-handling schemes within the control hardware and/or algorithm of a given appli- cation based on the indicated fault(s) and the velocity or position data provided by the ad2s1205. false null condition resolver-to-digital converters that employ type ii tracking loops based on the previously stated error equation (see equation 4 in the theory of operation section) can suffer from a condition known as a false null. this condition is caused by a metastable solution to the error equation when ? ? = 180. the ad2s1205 is not susceptible to this condition because its hysteresis is implemented external to the tracking loop. as a result of the loop architecture chosen for the ad2s1205, the internal error signal constantly has some movement (1 lsb per clock cycle); therefore, in a metastable state, the converter moves to an unstable condition within one clock cycle. this causes the tracking loop to respond to the false null condition as if it were a 180 step change in input position (the response time is the same, as specified in the dynamic performance section of table 1 ). therefore, it is impossible to enter the metastable condition after the start-up sequence if the resolver signals are valid.
ad2s1205 rev. a | page 11 of 20 on-board programmable sinusoidal oscillator an on-board oscillator provides the sinusoidal excitation signal (exc) and its complement signal ( exc ) to the resolver. the fre- quency of this reference signal is programmable to four standard frequencies (10 khz, 12 khz, 15 khz, or 20 khz) by using the fs1 and fs2 pins (see ). fs1 and fs2 have internal pull-ups, so the default frequency is 10 khz. the amplitude of this signal is centered on 2.5 v and has an amplitude of 3.6 v p-p. table 5 table 5. excitation frequency selection frequency selection (khz) fs1 fs2 10 1 1 12 1 0 15 0 1 20 0 0 the frequency of the reference signal is a function of the clkin frequency. by decreasing the clkin frequency, the minimum excitation frequency can also be decreased. this allows an excitation frequency of 7.5 khz to be set when using a clkin frequency of 6.144 mhz, and it also decreases the maximum tracking rate to 750 rps. the reference output of the ad2s1205 requires an external buffer amplifier to provide gain and additional current to drive the resolver. see figure 6 for a suggested buffer circuit. the ad2s1205 also provides an internal synchronous reference signal that is phase locked to its sin and cos inputs. phase errors between the resolvers primary and secondary windings may degrade the accuracy of the rdc and are compensated for by using this synchronous reference signal. this also compensates for the phase shifts due to temperature and cabling, and it eliminates the need for an external preset phase-compensation circuit. synthetic reference generation when a resolver undergoes a high rotation rate, the rdc tends to act as an electric motor and produces speed voltages in addition to the ideal sin and cos outputs. these speed voltages are in quadrature to the main signal waveform. moreover, nonzero resistance in the resolver windings causes a nonzero phase shift between the reference input and the sin and cos outputs. the combination of the speed voltages and the phase shift causes a tracking error in the rdc that is approximated by frequency reference rate rotation shiftphase error = (6) to compensate for the described phase error between the resolver reference excitation and the sin/cos signals, an internal synthetic reference signal is generated in phase with the reference frequency carrier. the synthetic reference is derived using the internally filtered sin and cos signals. it is generated by determining the zero crossing of either the sin or cos (whichever signal is larger), which improves phase accuracy, and evaluating the phase of the resolver reference excitation. the synthetic reference reduces the phase shift between the reference and sin/cos inputs to less than 10 and can operate for phase shifts of 45. charge-pump output a 204.8 khz square wave output with a 50% duty cycle is available at the cpo pin of the ad2s1205. this square wave output can be used for negative rail voltage generation or to create a v cc rail. connecting the converter ground is connected to the agnd and dgnd pins (see figure 5 ). a positive power supply (v dd ) of 5 v dc 5% is connected to the av dd and dv dd pins, with typical values for the decoupling capacitors being 10 nf and 4.7 f. these capacitors are then placed as close to the device pins as possible and are connected to both av dd and dv dd . if desired, the reference oscillator frequency can be changed from the nominal value of 10 khz using fs1 and fs2. typical values for the oscillator decoupling capacitors are 20 pf, whereas typical values for the reference decoupling capacitors are 10 f and 0.01 f. as outlined in the loss of signal detection section 68 k resistors between the sin and sinlo inputs and the cos and coslo inputs can be used to ensure loss of signal detection when all four inputs from resolver are disconnected. in this recommended configuration, the converter introduces a v ref /2 offset in the sin and cos signal outputs from the resolver. the sinlo and coslo signals can each be connected to a different potential relative to ground if the sin and cos signals adhere to the recommended specifications. note that because the exc and exc outputs are differential, there is an inherent gain of 2. shows a suggested buffer circuit. capacitor c1 may be used in parallel with resistor r2 to filter out any noise that may exist on the exc and figure 6 exc outputs. care should be taken when selecting the cutoff frequency of this filter to ensure that phase shifts of the carrier caused by the filter do not exceed the phase lock range of the ad2s1205. the gain of the circuit is )) 1/(1()/( c1r2 r1r2ncarriergai + ? = (7) and ? ? ? ? ? ? +? ? ? ? ? ? ? ? ? ? ? ? ? += in ref out vc1r2 r1 r2 r1 r2 vv )) 1/(1( 1 (8) where: is the radian frequency of the applied signal. v ref , a dc voltage, is set so that v out is always a positive value, eliminating the need for a negative supply.
ad2s1205 rev. a | page 12 of 20 a separate screened twisted pair cable is recommended for analog inputs sin/sinlo and cos/coslo. the screens should terminate to either refout or agnd. 06339-005 dv dd 5v 1 2 3 4 5 6 7 8 9 10 11 reset 33 32 31 30 29 28 27 26 25 24 dgnd 8.192 mhz 20pf 20pf 4.7 f 10nf 23 12 13 14 15 dgnd 16 dv dd 17 18 19 20 21 22 44 refbyp 43 agnd 42 cos 41 coslo 40 av dd 39 sinlo 38 sin 37 agnd 36 35 exc 34 ad2s1205 exc 10 f 10nf 5v s2 s4 4.7 f 10nf s3 s1 5v buffer circuit buffer circuit r2 r1 68k ? 68k ? figure 5. connecting the ad2s1205 to a resolver 06339-017 c1 r2 r1 12v 12v 5v exc/exc (v in ) (v ref ) v out ad8662 figure 6. buffer circuit clock requirements to achieve the specified dynamic performance, an external crystal is recommended at the clkin and xtalout pins. the position and velocity accuracy are guaranteed for a frequency range of 8.192 mhz 25%. however, the velocity outputs are scaled in proportion to the clock frequency so that if the clock is 25% greater than the nominal, the full-scale velocity is 25% greater than nominal. the maximum tracking rate, tracking loop bandwidth, and excitation frequency also vary with the clock frequency. absolute position and velocity output the angular position and velocity are represented by binary data and can be extracted via either a 12-bit parallel interface or a 3-wire serial interface that operates at clock rates of up to 25 mhz. soe input the serial output enable pin ( soe ) is held high to enable the parallel interface and low to enable the serial interface. in the latter case, pin db0 to pin db9 are placed into a high impedance state while db11 is the serial output (so) and db10 is the serial clock input (sclk). data format the angular position data represents the absolute position of the resolver shaft as a 12-bit unsigned binary word. the angular velocity data is a 12-bit twos complement word, representing the velocity of the resolver shaft rotating in either a clockwise or counterclockwise direction. parallel interface the angular position and velocity are available on the ad2s1205 in two 12-bit registers, accessed via the 12-bit parallel port. the parallel interface is selected by holding the soe pin high. data is transferred from the velocity and position integrators to the position and velocity registers, respectively, after a high-to-low transition on the sample pin. the rdvel pin selects whether data from the position or velocity register is transferred to the output register. the cs pin must be held low to transfer data from the selected register to the output register. finally, the rd input is used to read the data from the output register and to enable the output buffer. the timing requirements for the read cycle are shown in . figure 7 sample input data is transferred from the position and velocity integrators to the position and velocity registers, respectively, after a high-to- low transition on the sample signal. this pin must be held low for at least t 1 to guarantee correct latching of the data. rd should not be pulled low before this time because data will not be ready. the converter continues to operate during the read process. a rising edge of sample resets the internal registers that contain the minimum and maximum magnitude of the monitor signal.
ad2s1205 rev. a | page 13 of 20 rd input cs input the 12-bit data bus lines are normally in a high impedance state. the output buffer is enabled when cs and rd are held low. a falling edge of the rd signal transfers data to the output buffer. the selected data is made available to the bus to be read within t 6 of the rd pin going low. the data pins return to a high impedance state when the rd pin returns to a high state within t 7 . when reading data continuously, wait a minimum of t 3 after rd is released before reapplying it. the device is enabled when cs is held low. rdvel input rdvel input is used to select between the angular position register and the angular velocity register, as shown in . figure 7 rdvel is held high to select the angular position register and low to select the angular velocity register. the rdvel pin must be set (stable) at least t 4 before the rd pin is pulled low. 06339-007 t 3 t 6 t 7 f clkin clkin data don't care velocity position t 2 sample cs rd rdvel t 1 t 1 t 3 t 5 t 4 t 5 t 4 t 7 t 6 figure 7. parallel port read timing table 6. parallel port timing parameter description in typ ax nit f clkin frequency of clock input 6.144 8.192 10.24 mhz t 1 sample pulse width 2 (1/f clkin ) + 20 ns t 2 delay from sample before rd / cs low 6 (1/f clkin ) + 20 ns t 3 rd pulse width 18 ns t 4 set time rdvel before rd / cs low 5 ns t 5 hold time rdvel after rd / cs low 7 ns t 6 enable delay rd / cs low to data valid 30 ns t 7 disable delay rd / cs low to data high-z 18 ns
ad2s1205 rev. a | page 14 of 20 serial interface the angular position and velocity are available on the ad2s1205 in two 12-bit registers. these registers can be accessed via a 3-wire serial interface (so, rd , and sclk) that operates at clock rates of up to 25 mhz and is compatible with spi and dsp interface standards. the serial interface is selected by holding the soe pin low. data from the position and velocity integrators are first trans- ferred to the position and velocity registers using the sample pin. the rdvel pin selects whether data is transferred from the position or velocity register to the output register, and the cs pin must be held low to transfer data from the selected register to the output register. finally, the rd input is used to read the data that is clocked out of the output register and is available on the serial output pin (so). when the serial interface is selected, db11 is used as the serial output pin (so), db10 is used as the serial clock input (sclk), and pin db0 to pin db9 are placed into the high imped- ance state. the timing requirements for the read cycle are described in . figure 8 so output the output shift register is 16 bits wide. data is clocked out of the device as a 16-bit word by the serial clock input (sclk). the timing diagram for this operation is shown in figure 8 . the 16-bit word consists of 12 bits of angular data (position or velocity, depending on rdvel input), one rdvel status bit, and three status bits (a parity bit, a degradation of signal bit, and a loss of tracking bit). data is clocked out msb first from the so pin, beginning with db15. db15 through db4 correspond to the angular information. the angular position data format is unsigned binary, with all 0s corresponding to 0 and all 1s cor- responding to 360 ? l lsb. the angular velocity data format is twos complement, with the msb representing the rotation direction. db3 is the rdvel status bit, with a 1 indicating position and a 0 indicating velocity. db2 is dos, the degradation of signal flag (refer to the section). bit 1 is lot, the loss of tracking flag (refer to the section). bit 0 is par, the parity bit. the position and velocity data are in odd parity format, and the data readback always contains an odd number of logic highs (1s). fault detection circuit fault detection circuit sample input data is transferred from the position and velocity integrators to the position and velocity registers, respectively, after a high-to- low transition on the sample signal. this pin must be held low for at least t 1 to guarantee correct latching of the data. rd should not be pulled low before this time because data will not be ready. the converter continues to operate during the read process. cs input the device is enabled when cs is held low. rd input the 12-bit data bus lines are normally in a high impedance state. the output buffer is enabled when cs and rd are held low. the rd input is an edge-triggered input that acts as a frame synchronization signal and an output enable. on a falling edge of the rd signal, data is transferred to the output buffer. data is then available on the serial output pin (so); however, it is only valid after rd is held low for t 9 . the serial data is clocked out of the so pin on the rising edges of sclk, and each data bit is available at the so pin on the falling edge of sclk. however, as the msb is clocked out by the falling edge of rd , the msb is available at the so pin on the first falling edge of sclk. each subsequent bit of the data-word is shifted out on the rising edge of sclk and is available at the so pin on the falling edge of sclk for the next 15 clock pulses. the high-to-low transition of rd must occur during the high time of the sclk to avoid db14 being shifted on the first rising edge of the sclk, which would result in the msb being lost. rd may rise high after the last falling edge of sclk. if rd is held low and additional sclks are applied after db0 has been read, then 0s will be clocked from the data output. when reading data continuously, wait a minimum of t 5 after rd is released before reapplying it. rdvel input rdvel input is used to select between the angular position register and the angular velocity register. rdvel is held high to select the angular position register and low to select the angular velocity register. the rdvel pin must be set (stable) at least t 4 before the rd pin is pulled low.
ad2s1205 rev. a | page 15 of 20 t 11 t sclk t 10 t 9 t 8 06339-008 sclk so msb msb ? 1 lsb rdvel dos lot par rd t 3 t 6 t 7 f clkin clkin so velocity position t 2 s ample cs rd rdvel t 1 t 1 t 3 t 5 t 4 t 5 t 4 t 7 t 6 figure 8. serial port read timing table 7. serial port timing 1 parameter description min typ max unit t 8 msb read time rd / cs to sclk 15 t sclk ns t 9 so enable time rd / cs to db valid 30 ns t 10 data access time, sclk to db valid 30 ns t 11 bus relinquish time rd / cs to so high-z 18 ns t sclk serial clock period (25 mhz maximum) 40 ns 1 t 1 to t 7 are as defined in table 6.
ad2s1205 rev. a | page 16 of 20 incremental encoder outputs the a, b, and nm incremental encoder emulation outputs are free running and are valid if the resolver format input signals applied to the converter are valid. the ad2s1205 emulates a 1024-line encoder, meaning that, in terms of the converter resolution, one revolution produces 1024 a and b pulses. pulse a leads pulse b for increasing angular rotation (clockwise direction). the addition of the dir output negates the need for external a and b direction decode logic. the dir output indicates the direction of the input rotation and is high for increasing angular rotation. dir can be considered an asyn- chronous output that can make multiple changes in state between two consecutive lsb update cycles. this occurs when the direction of the rotation of the input changes but the magnitude of the rotation is less than 1 lsb. the north marker pulse is generated as the absolute angular position passes through zero. the north marker pulse width is set internally for 90 and is defined relative to the a cycle. figure 9 details the relationship between a, b, and nm. 06339-009 a b nm figure 9. a, b, and nm timing for clockwise rotation unlike incremental encoders, the ad2s1205 encoder output is not subject to error specifications such as cycle error, eccentricity, pulse and state width errors, count density, and phase ?. the maximum speed rating (n) of an encoder is calculated from its maximum switching frequency (f max ) and its pulses per revo- lution (ppr). ppr f n max = 60 (9) the a and b pulses of the ad2s1205 are initiated from the inter- nal clock frequency, which is exactly half the external clkin frequency. with a nominal clkin frequency of 8.192 mhz, the internal clock frequency is 4.096 mhz. the equivalent encoder switching frequency is )pulse1updates4(mhz024.1mhz096.44/1 = = (10) for 12 bits, the ppr is 1024. therefore, the maximum speed (n) of the ad2s1205 with a clkin of 8.192 mhz is rpm000,60 1024 000,024,160 = = n (11) to achieve the maximum speed of 75,000 rpm, select an external clkin of 10.24 mhz to produce an internal clock frequency equal to 5.12 mhz. this compares favorably with encoder specifications, which state f max as 20 khz (photo diodes) to 125 khz (laser based), depending on the type of light system used. a 1024-line laser- based encoder has a maximum speed of 7300 rpm. the inclusion of a and b outputs allows an ad2s1205 and resolver-based solution to replace optical encoders directly without the need to change or upgrade the users existing application software. supply sequencing and reset the ad2s1205 requires an external reset signal to hold the reset input low until v dd is within the specified operating range of 4.5 v to 5.5 v. the reset pin must be held low for a minimum of 10 s after v dd is within the specified range (shown as t rst in ). applying a figure 10 reset signal to the ad2s1205 initializes the output position to a value of 0x000 (degrees output through the parallel, serial, and encoder interfaces) and causes los to be indicated (lot and dos pins pulled low), as shown in . figure 10 failure to apply the correct power-up/reset sequence may result in an incorrect position indication. after a rising edge on the reset input, the device must be allowed at least 20 ms (shown as t track in ) for the internal circuitry to stabilize and the tracking loop to settle to the step change of the input position. after t track , a figure 10 sample pulse must be applied, which in turn releases the lot and dot pins to the state determined by the fault detection circuitry and provides valid position data at the parallel and serial outputs. (note that if position data is acquired via the encoder outputs, it can be monitored during t track .) the reset pin is then internally pulled up. t rst t rst 0 6339-010 v dd reset 4.75v valid output data s ample lot dos t track figure 10. power supply sequencing and reset
ad2s1205 rev. a | page 17 of 20 circuit dynamics loop response model 0 6339-011 error (acceleration) ? in out velocity k1 k2 1 ? z ?1 1 ? bz ?1 1 ? z ?1 c 1 ? az ?1 c sin/cos lookup figure 11. rdc system response block diagram the rdc is a mixed-signal device that uses two adcs to digitize signals from the resolver and a type ii tracking loop to convert these to digital position and velocity words. the first gain stage consists of the adc gain on the sin/cos inputs and the gain of the error signal into the first integrator. the first integrator generates a signal proportional to velocity. the compensation filter contains a pole and a zero that are used to provide phase margin and reduce high frequency noise gain. the second integrator is the same as the first and generates the position output from the velocity signal. the sin/cos lookup has unity gain. the values for each section are as follows: adc gain parameter (k1 nom = 1.8/2.5) )v( )v( p ref in v v k2 = (12) error gain parameter = 21018 6 k2 (13) compensator zero coefficient 4096 4095 = a (14) compensator pole coefficient 4096 4085 = b (15) integrator gain parameter 000,096,4 1 = c (16) int1 and int2 transfer function 1 1 )( ? ? = z c zi (17) compensation filter transfer function 1 1 1 1 )( ? ? ? ? = bz az zc (18) r2d open-loop transfer function )()( )( 2 zczik2k1zg = (19) r2d closed-loop transfer function )(1 )( )( zg zg zh + = (20) the closed-loop magnitude and phase responses are that of a second-order low-pass filter (see figure 12 and figure 13 ). to convert g(z) into the s-plane, an inverse bilinear transfor- mation is performed by substituting the following equation for z : s t s t z ? + = 2 2 (21) where t is the sampling period (1/4.096 mhz 244 ns). substitution yields the open-loop transfer function g(s). )1(2 )1( 1 )1(2 )1( 1 4 1 )1( )( 2 22 b bt s a at s s ts st ba ak2k1 sg ? + + ? + + ++ ? ? = (22) this transformation produces the best matching at low frequencies ( f < f sample ). at such frequencies (within the closed-loop bandwidth of the ad2s1205), the transfer function can be simplified to 2 1 2 1 1 )( st st s k sg a + + ? (23) where: ba ak2k1 k b bt t a at t a ? ? = ? + = ? + = )1( )1(2 )1( )1(2 )1( 2 1 solving for each value gives t 1 = 1 ms, t 2 = 90 s, and k a 7.4 10 6 s ?2 . note that the closed-loop response is described as )(1 )( )( sg sg sh + = (24) by converting the calculation to the s-domain, it is possible to quantify the open-loop dc gain (k a ). this value is useful to calculate the acceleration error of the loop (see the sources of error section).
ad2s1205 rev. a | page 18 of 20 the step response to a 10 input step is shown in figure 14 . because the error calculation (see equation 2) is nonlinear for large values of ? ?, the response time for such large (90 to 180) step changes in position typically takes three times as long as the response to a small (<20) step change in position. in response to a step change in velocity, the ad2s1205 exhibits the same response characteristics as it does for a step change in position. 06339-012 1 5 0 ?40 ?35 ?30 ?25 ?20 magnitude (db) ?15 ?10 ?5 ?45 10 100 10k 1k frequency (hz) 100k figure 12. rdc system magnitude response 06339-013 1 0 ?20 ?180 ?160 ?140 ?120 ?100 phase (degrees) ?80 ?60 ?40 ?200 10 100 10k 1k frequency (hz) 100k figure 13. rdc system phase response 06339-014 0 20 18 2 4 6 8 10 angle (degrees) 12 14 16 0 12 4 3 time (ms) 5 figure 14. rdc small step response sources of error acceleration a tracking converter employing a type ii servo loop does not have a lag in velocity. there is, however, an error associated with acceleration. this error can be quantified using the acceleration constant (k a ) of the converter. error tracking onaccelerati input k a = (25) conversely, a k onaccelerati input error tracking = (26) figure 15 shows tracking error vs. acceleration for the ad2s1205. the units of the numerator and denominator must be consistent. the maximum acceleration of the ad2s1205 is defined as the acceleration that creates an output position error of 5 (that is, when lot is indicated). the maximum acceleration can be calculated as 2 2 rps000,103 )/rev(360 5)(sec ? = ? (27) 06339-015 0 10 9 1 2 3 4 5 tracking error (degrees) 6 7 8 0 40k 80k 160k 120k acceleration (rps 2 ) 200k figure 15. tracking error vs. acceleration
ad2s1205 rev. a | page 19 of 20 connecting to the dsp the ad2s1205 serial port is ideally suited for interfacing to dsp- configured microprocessors. figure 16 shows the ad2s1205 interfaced to an admc401, one of the dsp-based motor controllers. the on-chip serial port of the admc401 is used in the following configuration ? alternate framing transmit mode with internal framing (internally inverted) ? normal framing receive mode with external framing (internally inverted) ? internal serial clock generation in this configuration, the internal tfs signal of admc401 is used as an external rfs to fully control the timing of data received, and the same tfs is connected to rd of the ad2s1205. in addition, the admc401 provides an internal continuous serial clock to the ad2s1205. the sample signal on the ad2s1205 can be provided either by using a pio or by inverting the pwmsync signal to synchronize the position and velocity readings with the pwm switching frequency. cs and rdvel can be obtained using two pio outputs of the admc401. the 12 bits of significant data and the status bits are available on each consecutive negative edge of the clock after the rd signal goes low. data is clocked from the ad2s1205 into the data receive register of the admc401. this is internally set to 16 bits (12 data bits, 4 status bits) because 16 bits are received overall. the serial port automatically generates an internal processor interrupt. this allows the admc401 to read all 16 bits and then continue to process data. all admc401 products can interface to the ad2s1205 by using similar interface circuitry. 06339-016 sclk dr tfs rfs pwmsync pio pio sclk soe so rd sample cs rdvel admc401 ad2s1205 figure 16. connecting to the admc401
ad2s1205 rev. a | page 20 of 20 outline dimensions compliant to jedec standards ms-026-bcb view a top view (pins down) 11 1 44 34 33 23 22 12 1.60 max 0.75 0.60 0.45 0.45 0.37 0.30 pin 1 0.20 0.09 1.45 1.40 1.35 0.10 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 0.80 bsc lead pitch 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 051706-a figure 17. 44-lead low profile quad flat package [lqfp] (st-44-1) dimensions shown in millimeters ordering guide model 1 , 2 temperature range angular accuracy package description package option ad2s1205ystz ?40c to +125c 11 arc min 44-lead lo w profile quad flat package [lqfp] st-44-1 adw71205ystz ?40c to +125c 11 arc min 44-lead lo w profile quad flat package [lqfp] st-44-1 ad2s1205wstz ?40c to +125c 22 arc min 44-lead lo w profile quad flat package [lqfp] st-44-1 ADW71205WSTZ ?40c to +125c 22 arc min 44-lead low profile quad flat package [lqfp] st-44-1 ADW71205WSTZ-rl ?40c to +125c 22 arc min 44-lead low profile quad flat package [lqfp] st-44-1 eval-ad2s1205cbz 3 evaluation board eval-control brd2 4 controller board 1 z = rohs compliant part. 2 w = qualified for auto motive applications. 3 this can be used either as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation /demonstration purposes. 4 evaluation board controller. this board is a complete unit that allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designator. for a complete evalua tion kit, order the adc evaluati on board (that is, the eval-ad2 s1205cbz), the eval-control brd 2, and a 12 v ac transformer. automotive products the ad2s1205 models are available with controlled manufacturing to support the quality and reliability requirements of automoti ve applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06339-0-5/10(a)

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